1. Field of Invention
This application relates generally to test and measurement equipment and more specifically to calibration of systems for making time dependent measurements.
2. Discussion of Related Art
Automated test equipment (a “tester”) is widely used in the manufacture of semiconductor devices. Devices are tested at least once, and often multiple times, during their manufacture. The results of the test can be used to remove defective devices from the stream of devices being manufactured. In some cases, test results reveal improperly operating manufacturing equipment and can be used to increase the yield of semiconductor devices by identifying process corrections. In other cases, the test results reveal corrections that can be made to the devices under test. For example, memories, programmable array logic devices and similar devices often contain redundant structures. If testing reveals that one structure is defective, the device can be modified to substitute a redundant structure for the defective one. In other situations, the test results can be used for “binning” the parts. A device that does not meet its intended operating specifications, but does operate properly against degraded specifications, might be packaged and sold at a lower price with lower performance specifications. For example, a device might exhibit errors when operating at a high speed, but perform properly when operated at a lower speed. Similarly, a device might exhibit errors when operated at the high end of its temperature range, but perform adequately at a lower temperature. These devices could be packaged and sold with indications that their maximum operating speed or temperature is lower than the design specification.
To detect errors in operation of semiconductor devices, automatic test equipment applies stimulus signals to the device and measures response signals. Test equipment includes many “channels.” Each channel can, in any cycle, either generate or measure a digital value to be applied to one test point on the device under test. Channels might include additional circuitry that can generate or measure other kinds of signals. For example, some channels contain circuitry that generates a continuous clock of a programmed frequency or circuitry that measures the time difference between successive pulses.
FIG. 1 illustrates, in greatly simplified form, a tester 100. Tester 100 is shown testing a device under test (DUT) 110. Tester 100 contains a central controller 120. Controller 120 might include a computer work station that serves as an operator interface to allow a user to develop or load test programs into the tester. Controller 120 might also include a tester body that provides centralized resources that are used by multiple channels or are not related to circuitry in the channels, but details of such known features are omitted for simplicity.
Tester 100 includes multiple channels, 1301, 1302, . . . 130N. Taking channel 1301 as representative, each channel can has a pattern generator 140 and a timing generator 150. Pattern generator 140 is programmed to specify, for each cycle during a test, what the circuitry within channel 1301 should do. For example, it might specify a value to drive to DUT 110 or what value is expected from DUT 110.
Timing generator 150 produces timing signals that control the times at which signal transitions occur. For example, a timing signal might specify the beginning of a signal being generated or the time at which a signal value is compared to an expected value. To fully test DUT 110, it is important to control the times at which stimulus signals are applied and the times at which the responses are measured. Timing generator 150 provides signals that control these functions.
Channel 1301 also includes pin electronics 160. Pin electronics 160 contains the circuitry that drives the line 1701 connected to DUT 110 or measures the signal value on that line.
To drive line 1701, pin electronics 160 includes a driver 162. Driver 162 is connected to a flip-flop 164. Flip-flop 164 is in turn clocked by a signal from timing generator 150. The data input to flip-flop 164 is provided by pattern generator 140. Flip-flop 164 causes a value specified by pattern generator 140 to be driven onto line 1701 at a time specified by timing generator 150. Flip-flop 164 might be termed a “formatter.” Formatters are known in the art and a full formatter, including all of the features commonly found in a tester, is not shown for simplicity.
To sense a signal on line 1701, pin electronics 160 includes a comparator 166. One input of comparator 166 is connected to line 1701. A reference input of comparator 166 is coupled to a programmable reference value generator—typically a register storing a digital input that is applied to a digital to analog converter. The output of comparator 166 is provided to a latch 180. Latch 180 is controlled by a timing signal generated by timing generator 150. The data output of latch 180 is provided to pattern generator 140. In this way, pin electronics 160 indicates whether the value on line 1701 has a particular value at a time dictated by signals from timing generator 150. As with the driver portion of pin electronics 160, the comparator portion is well known in the art and a simplified version is shown.
Timing generator 150 provides signals that control the relative timing of signals at pin electronics 160. To accurately measure the performance of DUT 110, it is necessary to relate the times at which signals are generated or measured at pin electronics 160 to the times those signals reach or leave DUT 110. The transit time through line 1701 must be considered.
To compensate for this transit time, a tester is typically calibrated. To calibrate a tester, measurements are made to determine the transit time through line 1701. Programmed time values are offset by an amount to compensate for the transit time through line 1701. With calibration, the signals generated or measured at pin electronics 160 are an accurate indication of signals at DUT 110.
One way in which the transit time through line 1701 is measured is through a technique called Time Domain Reflectometry (TDR). TDR is illustrated in FIG. 2. To make a TDR measurement, test equipment 100 transmits a pulse 210 on line 1701. The pulse is transmitted at a time t=0, as indicated at A.
Pulse 210 travels down line 1701 until it reaches the end of the line at some time later, indicated at B as t=X. When the line is un-terminated or terminated in a short or any other load that is not matched to the impedance of the line, some or all of the pulse will reflect back towards test equipment 100. As shown at C, pulse 210 begins to travel back towards test equipment 100.
As shown at D, at time t=2×, pulse 210 reaches test equipment 100. By detecting the time of the reflected pulse relative to the time that the pulse was transmitted, test equipment 100 can determine the transit time through line 1701.
FIGS. 3A . . . 3B illustrate a measurement technique by which tester 100 may determine the time of an edge of a signal, which might be used to determine the time of arrival of a pulse. This technique is sometimes called an “edge find” technique. The tester is programmed with a threshold H in register 168 (FIG. 1). The tester emits a pulse at a time that can be taken to be t=0. At some time later, latch 180 latches the output of comparator 166.
As illustrated in FIG. 3A, the tester issues the latch command at a time T1 relative to the transmission of the pulse. Latching comparator 166 at time T1 has the effect of a very coarse measurement of the value of the signal on line 1701 in the window 312A. From this single comparison, tester 100 may determine whether the signal at time T1 is above or below threshold H.
In the window 312A, the pulse 310 has not reached tester 100 and the signal on line 1701 is below the threshold H. Accordingly, tester 100 determines that at time T1, the signal on line 1701 is LO, which is interpreted as an indication that pulse 310 has not yet reached pin electronics 160.
Another pulse is then transmitted at a time which may again be considered time t=0. FIG. 3B illustrates a measurement made at a time T1+D relative to the transmission of the pulse. In measurement window 312B, pulse 310 has not reached tester 100 and the signal is again below the threshold H. This measurement is indicated by a logical LO latched at the output of comparator 166.
FIG. 3C illustrates a measurement made at a time T1+2D relative to the transmission of another pulse. In the measurement window 312C, the pulse 310 has reached tester 100 and the signal is above the threshold H. Tester 100 indicates this signal level as a logical HI.
This series of measurements allows tester 100 to determine that a pulse 310 transmitted by tester 100 will reflect and reach tester 100 at a time between T1+D and T1+2D after it is transmitted. This information allows calculation of the signal transit time through line 1701. The signal transmit time allows tester 100 to be calibrated to remove any errors in time measurements caused by signal delays in line 1701.
Calibration using TDR is very convenient because TDR measurements are made using circuitry that is in tester 100 for testing DUT 110. However, the calibration indicates that pulse 310 arrived at some time between T1+D and T1+2D. If D is the smallest increment at which timing generator 150 can specify test signals, this value limits the resolution of calibration measurements. It would be desirable to calibrate a tester with as much precision as possible. It would also be desirable to calibrate a tester using circuitry that is be present in a tester for other measurements.
FIG. 4 is a sketch of programmable clock generation circuitry, such as might be found in a tester, but has not heretofore been used for timing calibration. Clock generation circuit 400 uses a technique sometimes called direct digital synthesis (DDS) to generate a clock, CLOCK_L, that has a programmable frequency. Clock generation circuit 400 is clocked by a clock signal MCLK. MCLK is usually a fixed frequency clock. It is made to be relatively low frequency, around 100 MHz, so that it can be accurately distributed throughout tester 100. More details of the design and use of such a clock generation circuit may be found in U.S. Pat. No. 6,188,253 to Gage, et al., entitled ANALOG CLOCK MODULE, which is hereby incorporated by reference in its entirety.
Clock generation circuit 400 includes a Numeric Counter Oscillator (NCO) 410. More details of design and use of an NCO may be found in pending U.S. patent application Ser. No. 10/748,488, filed Dec. 29, 2003, which is hereby incorporated by reference in its entirety.
NCO 410 includes an accumulator 420. Accumulator 420 includes a register 422 that is clocked by MCLK. The input of register 422 comes from adder 424. Adder 424 computes the sum of the value previously stored in register 422 and a value stored in a register 426.
The output of accumulator 420 is used to address a memory denoted sine table 430. Sine table 430 stores a sequence of samples of a periodic signal, usually a sine wave. As the values in accumulator 420 increase, the sine table outputs samples that correspond to points on that sine wave. The values in the sequence represent points on the sine wave that are successively later in phase. Thus, the value in accumulator 420 indicates the phase of the sine wave at a particular point in time.
The value in register 426 indicates the amount by which the phase increases from sample to sample. Accordingly, changing the value in register 426 changes the rate of the change of the phase, i.e., frequency, of the output waveform.
The samples of a sine wave provided by sine table 430 are input to digital to analog converter 432. The analog output of converter 432 is applied to filter 434. Filter 434 is a smoothing filter, creating an analog signal which is as close to a pure sine wave as is practical.
The sine wave is then supplied to clipping amplifier 436. Clipping amplifier 436 is a high gain amplifier that turns the sine wave into a square wave.
The square wave out of clipping amplifier 436 can serve as a digital clock with a frequency that can be programmed by changing the value in register 426. However, NCO 420 has a limited resolution with which a frequency can be programmed. The resolution depends on factors such as the number of bits of resolution of register 426 and the number of samples of a sine wave stored in sine table 430.
Where greater resolution is desired, a frequency scaling circuit 440 can be used. Often, a phase locked loop (PLL) is used as a frequency multiplier. The phase locked loop can multiply the frequency by an integer amount, which can be programmed. A counter can be used as a frequency divider. A counter can divide the frequency by an integer amount, which also can be programmed. A frequency multiplier and frequency divider can be used together to scale the frequency out of NCO by non-integer amounts equal to the ratio between the frequency multiplication provided by the PLL and the frequency division by the counter.
The block diagram of FIG. 4 is a simplified block diagram of a clock generation circuit. Conventional elements of such a circuit are not expressly shown. For example, circuitry to load register 426 is not shown. Likewise, circuitry to reset or load accumulator register 422 is not shown. However, such circuitry would be routinely included in a clock generation circuit of the type pictured.
While clock generation circuits as shown in FIG. 4 are known, such circuits have not heretofore been used in the manner described below. Moreover, it would be highly desirable to provide time measurements with very high precision and particularly advantageous to make high resolution measurements with circuitry as conventionally found in a tester.